Flash Status Register (Flash_Sr) - ST STM32F423 Reference Manual

Embedded Flash memory interface
3.8.4

Flash status register (FLASH_SR)

The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
Bits 15:9 Reserved, must be kept cleared.
Bit 8 RDERR: Read Protection Error (PCROP)
Bit 7 PGSERR: Programming sequence error
Bit 6 PGPERR: Programming parallelism error
Bit 5 PGAERR: Programming alignment error
Bit 4 WRPERR: Write protection error
84/1324
27 26 25
Res. Res. Res. Res.
11 10 9
Res. Res. Res. RDERR PGSERR PGPERR PGAERR WRPERR
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Set by hardware when an address to be read through the Dbus belongs to a read protected
part of the flash.
Reset by writing 1.
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
24 23 22
Res. Res.
8 7 6
rw rc_w1 rc_w1
RM0430 Rev 8
21 20 19
Res. Res. Res.
5 4 3
Res.
rc_w1 rc_w1
RM0430
18 17 16
Res. Res. BSY
r
2 1 0
Res. OPERR EOP
rc_w1 rc_w1