Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1408

FBSTP—Store BCD Integer and Pop (Continued)
FPU Flags Affected
C1
C0, C2, C3
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Floating-point Exceptions
#IS
#IA
#P
Protected Mode Exceptions
#GP(0)
#SS(0)
#NM
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
#NM
4:106
Set to 0 if stack underflow occurred.
Indicates rounding direction if the inexact exception (#P) is
generated: 0 = not roundup; 1 = roundup.
Undefined.
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Stack underflow occurred.
Source operand is empty; contains a NaN, , or unsupported
format; or contains value that exceeds 18 BCD digits in length.
Value cannot be represented exactly in destination format.
If a segment register is being loaded with a segment selector that
points to a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
EM or TS in CR0 is set.
Volume 4: Base IA-32 Instruction Reference