Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1122
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pshladd — Parallel Shift Left and Add
(
) pshladd2
Format:
qp
The four signed 16-bit data elements of GR
Description:
by count
2
16-bit data elements of GR
if the result of either the shift or the add is not representable as a signed 16-bit value,
the final result is saturated. The four signed 16-bit results are placed in GR
operand can be shifted by 1, 2 or 3 bits.
Operation:
if (PR[qp]) {
check_target_register(r
x[0] = GR[r
x[1] = GR[r
x[2] = GR[r
x[3] = GR[r
max = sign_ext(0x7fff, 16);
min = sign_ext(0x8000, 16);
for (i = 0; i < 4; i++) {
temp[i] = sign_ext(x[i], 16) << count
if (temp[i] > max)
else if (temp[i] < min)
else {
}
}
GR[r
] = concatenate4(res[3], res[2], res[1], res[0]);
1
GR[r
].nat = GR[r
1
}
Illegal Operation fault
Interruptions:
Volume 3: Instruction Reference
=
, count
,
r
r
r
1
2
2
3
bits (shifting zeros into the low-order bits), and added to the four signed
. Both the left shift and the add operations are saturating:
r
3
);
1
]{15:0};
y[0] = GR[r
2
]{31:16};
y[1] = GR[r
2
]{47:32};
y[2] = GR[r
2
]{63:48};
y[3] = GR[r
2
res[i] = max;
res[i] = min;
res[i] = temp[i] + sign_ext(y[i], 16);
if (res[i] > max)
res[i] = max;
if (res[i] < min)
res[i] = min;
].nat || GR[r
2
are each independently shifted to the left
r
2
]{15:0};
3
]{31:16};
3
]{47:32};
3
]{63:48};
3
;
2
].nat;
3
pshladd
A10
. The first
r
1
3:223
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