Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1867

PEXTRW: Extract Word
Opcode
0F,C5, /r, ib
Operation: sel = imm8 & 0x3;
mm_temp = (mm >> (sel * 16)) & 0xffff;
r[15-0] = mm_temp[15-0];
r[31-16] = 0x0000;
The PEXTRW instruction moves the word in MM selected by the two least significant bits
Description:
of imm8 to the lower half of a 32-bit integer register.
None.
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a pending FPU
exception.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Volume 4: IA-32 SSE Instruction Reference
Instruction
PEXTRW r32, mm, imm8
Disabled FP Register Fault if PSR.dfl is 1
Description
Extract the word pointed to by imm8 from MM and move it to a
32-bit integer register.
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