Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1566

LGDT/LIDT—Load Global/Interrupt Descriptor Table Register
Opcode
0F 01 /2
0F 01 /3
Description
Loads the values in the source operand into the global descriptor table register (GDTR)
or the interrupt descriptor table register (IDTR). The source operand is a pointer to 6
bytes of data in memory that contains the base address (a linear address) and the limit
(size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor
table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the
6-byte data operand) and a 32-bit base address (upper 4 bytes of the data operand)
are loaded into the register. If the operand-size attribute is 16 bits, a 16-bit limit (lower
2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here, the
high-order byte of the operand is not used and the high-order byte of the base address
in the GDTR or IDTR is filled with zeros.
The LGDT and LIDT instructions are used only in operating-system software; they are
not used in application programs. They are the only instructions that directly load a
linear address (that is, not a segment-relative address) and a limit in protected mode.
They are commonly executed in real-address mode to allow processor initialization prior
to switching to protected mode.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,LGDT/LIDT);
IF instruction is LIDT
THEN
FI;
ELSE (* instruction is LGDT *)
IF OperandSize = 16
FI;
FI;
Flags Affected
None.
4:264
Instruction
LGDT m16&32
LIDT m16&32
IF OperandSize = 16
THEN
IDTR(Limit)  SRC[0:15];
IDTR(Base)  SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
IDTR(Limit)  SRC[0:15];
IDTR(Base)  SRC[16:47];
THEN
GDTR(Limit)  SRC[0:15];
GDTR(Base)  SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
GDTR(Limit)  SRC[0:15];
GDTR(Base)  SRC[16:47];
Description
Load m into GDTR
Load m into IDTR
Volume 4: Base IA-32 Instruction Reference