Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1040

fwb — Flush Write Buffers
( ) fwb
Format: qp
The processor is instructed to expedite flushing of any pending stores held in write or
Description:
coalescing buffers. Since this operation is a hint, the processor may or may not take
any action and actually flush any outstanding stores. The processor gives no indication
when flushing of any prior stores is completed. An fwb instruction does not ensure
ordering of stores, since later stores may be flushed before prior stores.
To ensure prior coalesced stores are made visible before later stores, software must
issue a release operation between stores (see
release operations).
This instruction can be used to help ensure stores held in write or coalescing buffers are
not delayed for long periods or to expedite high priority stores out of the processors.
Operation: if (PR[qp]) {
mem_flush_pending_stores();
}
None
Interruptions:
Volume 3: Instruction Reference
Table 4-15 on page 2:83
fwb
M24
for a list of
3:141