Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1237
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4.4.2.1
Line Prefetch
40
M13
Instruction
lfetch.excl. lfhint
lfetch.fault. lfhint
lfetch.fault.excl. lfhint
4.4.2.2
Line Prefetch – Increment by Register
40
M14
Instruction
lfetch. lfhint
lfetch.excl. lfhint
lfetch.fault. lfhint
lfetch.fault.excl. lfhint
4.4.2.3
Line Prefetch – Increment by Immediate
40
M15
lfetch. lfhint
lfetch.excl. lfhint
lfetch.fault. lfhint
lfetch.fault.excl. lfhint
4.4.3
Semaphores
The semaphore instructions are encoded in major opcode 4 along with the integer
load/store instructions. See
opcode extensions. These instructions have the same cache locality opcode hint
extension field in bits 29:28 (hint) as load instructions. See
Completer" on page
3:338
37 36 35
30 29 28 27 26
6
m
x
hint x
6
4
1
6
2
Operands
[ r
]
3
37 36 35
30 29 28 27 26
6
m
x
hint x
6
4
1
6
2
Operands
[ r
], r
3
2
37 36 35
30 29 28 27 26
7
s
x
hint i
6
4
1
6
2
Instruction
Operands
[ r
], imm
3
"Loads and Stores" on page 3:323
3:328.
20 19
r
3
1
7
Opcode
m
6
0
20 19
r
r
3
2
1
7
7
Opcode
m
6
1
20 19
r
imm
3
1
7
7
Opcode
7
9
6 5
14
Extension
x
x
hint
6
2D
See Table 4-41 on
0
2E
page 3:337
2F
13 12
6 5
7
Extension
x
x
hint
6
2C
2D
See Table 4-41 on
0
page 3:337
2E
2F
13 12
6 5
7b
7
Extension
x
hint
6
2C
2D
See Table 4-41 on
page 3:337
2E
2F
for a summary of the
Table 4-39, "Load Hint
Volume 3: Instruction Formats
0
qp
6
0
qp
6
0
qp
6
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