Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1257

Table 4-62.
Opcode
Bits 40:37
Most floating-point instructions have a 2-bit opcode extension field in bits 35:34 (sf)
which encodes the FPSR status field to be used.
assignments.
Table 4-63.
4.6.1 Arithmetic
The floating-point arithmetic instructions are encoded within major opcodes 8 – D using
a 1-bit opcode extension field (x) in bit 36 and a 2-bit opcode extension field (sf) in bits
35:34. The opcode and x assignments are shown in
Table 4-64.
x
Bit 36
0
1
The fixed-point arithmetic and parallel floating-point select instructions are encoded
within major opcode E using a 1-bit opcode extension field (x) in bit 36. The fixed-point
arithmetic instructions also have a 2-bit opcode extension field (x
assignments are shown in
Table 4-65.
Opcode
Bits 40:37
E
3:358
Reciprocal Approximation 1-bit Opcode Extensions
x
Bit 33
0
1
1
Floating-point Status Field Completer
sf
Bits 35:34
0
1
2
3
Floating-point Arithmetic 1-bit Opcode Extensions
8 9
fma F1 fma.d F1
fma.s F1 fpma F1
Table
Fixed-point Multiply Add and Select Opcode Extensions
x
Bit 36
0
0
1 xma.l F2
q
Bit 36
0
1
0
1
Table 4-63
Table
Opcode
Bits 40:37
A B
fms F1 fms.d
fms.s F1 fpms
4-65.
x
2
Bits 35:34
1
fselect
frcpa F6
frsqrta F7
fprcpa F6
fprsqrta F7
summarizes these
sf
.s0
.s1
.s2
.s3
4-64.
C
F1 fnma F1
F1 fnma.s F1
) in bits 35:34. These
2
2
F3
xma.hu F2 xma.h
Volume 3: Instruction Formats
D
fnma.d F1
fpnma F1
3
F2