Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1609

OUT—Output to Port (Continued)
(* or virtual-8086 mode with all I/O permission bits for I/O port cleared *)
FI;
IF (Itanium_System_Environment) THEN
DEST_VA = IOBase | (Port{15:2}<<12) | Port{11:0};
DEST_PA = translate(DEST_VA);
[DEST_PA]  SRC; (* Writes to selected I/O port *)
FI;
memory_fence();
[DEST_PA]  SRC; (* Writes to selected I/O port *)
memory_fence();
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
IA_32_Exception
IA_32_Exception
#GP(0)
Protected Mode Exceptions
#GP(0)
Real Address Mode Exceptions
None.
Virtual 8086 Mode Exceptions
#GP(0)
Volume 4: Base IA-32 Instruction Reference
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Debug traps for data breakpoints and single step
Alignment faults
Referenced Port is to an unimplemented virtual address or PSR.dt is
zero.
If the CPL is greater than (has less privilege) the I/O privilege level
(IOPL) and any of the corresponding I/O permission bits in TSS for
the I/O port being accessed is 1 and when CFLG.io is 1.
If any of the I/O permission bits in the TSS for the I/O port being
accessed is 1.
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