Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1664

SHLD—Double Precision Shift Left
Opcode
0F A4
0F A5
0F A4
0F A5
Description
Shifts the first operand (destination operand) to the left the number of bits specified by
the third operand (count operand). The second operand (source operand) provides bits
to shift in from the right (starting with bit 0 of the destination operand). The destination
operand can be a register or a memory location; the source operand is a register. The
count operand is an unsigned integer that can be an immediate byte or the contents of
the CL register. Only bits 0 through 4 of the count are used, which masks the count to a
value between 0 and 31. If the count is greater than the operand size, the result in the
destination operand is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the
destination operand. For a 1-bit shift, the OF flag is set if a sign change occurred;
otherwise, it is cleared. If the count operand is 0, the flags are not affected.
The SHLD instruction is useful for multi-precision shifts of 64 bits or more.
Operation
COUNT  COUNT MOD 32;
SIZE  OperandSize
IF COUNT = 0
THEN
no operation
ELSE
IF COUNT  SIZE
4:362
Instruction
SHLD r/m16,r16,imm8
SHLD r/m16,r16 ,CL
SHLD r/m32,r32,imm8
SHLD r/m32,r32 ,CL
THEN (* Bad parameters *)
DEST is undefined;
CF, OF, SF, ZF, AF, PF are undefined;
ELSE (* Perform the shift *)
CF  BIT[DEST, SIZE - COUNT];
(* Last bit shifted out on exit *)
FOR i  SIZE - 1 DOWNTO COUNT
DO
Bit(DEST, i)  Bit(DEST, i - COUNT);
OD;
FOR i  COUNT - 1 DOWNTO 0
Description
Shift r/m16 to left imm8 places while shifting bits from r16 in
from the right
Shift r/m16 to left CL places while shifting bits from r16 in from
the right
Shift r/m32 to left imm8 places while shifting bits from r32 in
from the right
Shift r/m32 to left CL places while shifting bits from r32 in from
the right
Volume 4: Base IA-32 Instruction Reference