Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1649

SAHF—Store AH into Flags
Opcode
9E
Description
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the
corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and
5 of register AH are ignored; the corresponding reserved bits (1, 3, and 5) in the
EFLAGS registers are set as shown in the "Operation" below
Operation
EFLAGS(SF:ZF:0:AF:0:PF:1:CF)  AH;
Flags Affected
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3,
and 5 of the EFLAGS register are set to 1, 0, and 0, respectively.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Exceptions (All Operating Modes)
None.
Volume 4: Base IA-32 Instruction Reference
Instruction Clocks
SAHF 2
Description
Loads SF, ZF, AF, PF, and CF from AH into
EFLAGS register
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