Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1451

FPATAN—Partial Arctangent
Opcode
D9 F3
Description
Computes the arctangent of the source operand in register ST(1) divided by the source
operand in register ST(0), stores the result in ST(1), and pops the FPU register stack.
The result in register ST(0) has the same sign as the source operand ST(1) and a
magnitude less than .
The following table shows the results obtained when computing the arctangent of
various classes of numbers, assuming that underflow does not occur.
Table 2-6.
ST(1)
Note:
Fmeans finite-real number.
There is no restriction on the range of source operands that FPATAN can accept.
Operation
ST(1)  arctan(ST(1) / ST(0));
PopRegisterStack;
FPU Flags Affected
C1
C0, C2, C3
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Volume 4: Base IA-32 Instruction Reference
Instruction
FPATAN
FPATAN Zeros and NaNs
 F
-•
 3  4  /2
-•
 F  to  2
-p
 0
-p -p
+  + 
+0
+  +  to  +  2
+F
+  +3  4 +  2
NaN NaN
Set to 0 if stack underflow occurred.
Indicates rounding direction if the inexact-result exception (#P) is
generated: 0 = not roundup; 1 = roundup.
Undefined.
Abort.
Description
Replace ST(1) with arctan(ST(1)  ST(0)) and pop the register
stack
ST(0)
 0
+0
 /2  /2
 /2  /2
 0
-p
+ 
+0
+  2 +  2
+  2 +  2
NaN NaN NaN
+ 
+F
 /2  /4
 2 to  0
-0
 0  0
+0 +0
+  2 to +0
+0
+  2 +  /4
NaN NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
NaN
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