Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1162

tf — Test Feature
( ) tf. .
Format: qp trel ctype p
The value (in the range of 32-63) selects the feature bit defined in
Description: imm
5
tested from the features vector in CPUID[4]. See
Identification Registers" on page 1:34
forms a single-bit result either complemented or not depending on the trel completer.
This result is written to the two predicate register destinations
result is written to the destinations is determined by the compare type specified by
ctype. See the Compare instruction and
The trel completer values .nz and .z indicate non-zero and zero sense of the test. For
normal and unc types, only the .z value is directly implemented in hardware; the .nz
value is actually a pseudo-op. For it, the assembler simply switches the predicate
target specifiers and uses the implemented relation. For the parallel types, both
relations are implemented in hardware.
Table 2-55.
trel
nz
z
Table 2-56.
trel
nz
z
If the two predicate register destinations are the same (
predicate register), the instruction will take an Illegal Operation fault, if the qualifying
predicate is set or the compare type is unc.
Table 2-57.
imm
5
32
33
34 - 63
Volume 3: Instruction Reference
, =
p imm
1 2 5
for details on CPUID registers. The selected bit
Test Feature Relations for Normal and unc tf
Test Relation
selected feature available
selected feature unavailable
Test Feature Relations for Parallel tf
Test Relation
selected feature available
selected feature unavailable
Test Feature Features Assignment
Feature Symbol
@clz
@mpy
none
Section 3.1.11, "Processor
p
Table 2-15 on page 3:39.
z
and
p p
1
mpy4 , mpyshl4 feature
Not currently defined
tf
I30
Table 2-57 to be
and . The way the
p
1 2
Pseudo-op of
 p
p
1 2
specify the same
2
Feature
clz feature
3:263