Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1604

NOT—One's Complement Negation
Opcode
F6 /2
F7 /2
F7 /2
Description
Performs a bitwise NOT operation (1's complement) on the destination operand and
stores the result in the destination operand location. The destination operand can be a
register or a memory location.
Operation
DEST  NOT DEST;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
4:302
Instruction Description
NOT r/m8 Reverse each bit of r/m8
NOT r/m16 Reverse each bit of r/m16
NOT r/m32 Reverse each bit of r/m32
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If the destination operand points to a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
Volume 4: Base IA-32 Instruction Reference