Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1816

Exponent
all 1's
1
1
1
1
For all legal combinations above
The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the
significand. The M-bit is defined to be the most significant bit of the fractional portion of
the significand (i.e. the bit immediately to the right of the decimal place).
When the M-bit is the most significant bit of the fractional portion of the significand, it
must be 0 if the fraction is all 0's.
If the FXSAVE instruction is immediately preceded by an FP instruction which does not
use a memory operand, then the FXSAVE instruction does not write/update the DP
field, in the FXSAVE image.
MXCSR holds the contents of the SSE Control/Status Register. See the LDMXCSR
instruction for a full description of this field.
The fields XMM0-XMM7 contain the content of registers XMM0-XMM7 in exactly the
same format as they exist in the registers.
The SSE fields in the save image (XMM0-XMM7 and MXCSR) may not be loaded into the
processor if the CR4.OSFXSR bit is not set. This CR4 bit must be set in order to enable
execution of SSE instructions.
The destination m512byte is assumed to be aligned on a 16-byte boundary. If
m512byte is not aligned on a 16-byte boundary, FXSAVE generates a general protection
exception.
If #AC exception detection is disabled, a general protection exception is signalled if the
FP Exceptions:
address is not aligned on 16-byte boundary. Note that if #AC is enabled (and CPL is 3),
signalling of #AC is not guaranteed and may vary with implementation; in all
implementations where #AC is not signalled, a general protection fault will instead be
signalled. In addition, the width of the alignment check when #AC is enabled may also
vary with implementation; for instance, for a given implementation #AC might be
signalled for a 2-byte misalignment, whereas #GP might be signalled for all other
misalignments (4/8/16-byte). Invalid opcode exception if instruction is preceded by a
LOCK override prefix.
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF (fault-code) for a page
fault; #NM if CR0.EM = 1; #NM if TS bit in CR0 is set; #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3).
4:514
Exponent Fraction
all 0's all 0's
0 0
0 0
0 1
0 1
J and M
FTW valid bit
bits
1x 1
1x 1
00 1
10 1
0
Volume 4: IA-32 SSE Instruction Reference
x87 FTW
Special 10
Special 10
Special 10
Special 10
Empty 11