Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1053

ld
Operation: if (PR[qp]) {
size = fill_form ? 8 : (sixteen_byte_form ? 16 : sz);
speculative = (ldtype == 's' || ldtype == 'sa');
advanced = (ldtype == 'a' || ldtype == 'sa');
check_clear = (ldtype == 'c.clr' || ldtype == 'c.clr.acq');
check_no_clear = (ldtype == 'c.nc');
check = check_clear || check_no_clear;
acquire = (acquire_form || ldtype == 'acq' || ldtype == 'c.clr.acq');
otype = acquire ? ACQUIRE : UNORDERED;
bias = (ldtype == 'bias') ? BIAS : 0 ;
translate_address = 1;
read_memory = 1;
itype = READ;
if (speculative) itype |= SPEC ;
if (advanced) itype |= ADVANCE ;
if (size == 16) itype |= UNCACHE_OPT ;
if (sixteen_byte_form && !instruction_implemented(LD16))
illegal_operation_fault();
if ((reg_base_update_form || imm_base_update_form) && (r
illegal_operation_fault();
check_target_register(r
if (reg_base_update_form || imm_base_update_form)
check_target_register(r
if (reg_base_update_form) {
tmp_r2 = GR[r
tmp_r2nat = GR[r
}
if (!speculative && GR[r
register_nat_consumption_fault(itype);
defer = speculative && (GR[r
if (check && alat_cmp(GENERAL, r
translate_address = alat_translate_address_on_hit(ldtype, GENERAL,
r );
1
read_memory = alat_read_memory_on_hit(ldtype, GENERAL, r
}
if (!translate_address) {
if (check_clear || advanced)
} else {
if (!defer) {
3:154
);
1
);
3
];
2
].nat;
2
].nat)
3
alat_inval_single_entry(GENERAL, r
paddr = tlb_translate(GR[r
spontaneous_deferral(paddr, size, UM.be, mattr, otype,
if (!defer && read_memory) {
if (size == 16) {
mem_read_pair(&val, &val_ar, paddr, size, UM.be, mattr,
}
else {
// fault on NaT address
].nat || PSR.ed);// defer exception if spec
3
)) {
1
// remove any old alat entry
);
1
], size, itype, PSR.cpl, &mattr,
3
&defer);
bias | ldhint, &defer);
otype, ldhint);
== r ))
1 3
);
1
Volume 3: Instruction Reference