Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1250

The indirect branch instructions encoded within major opcodes 0 use a 3-bit opcode
extension field in bits 8:6 (btype) to distinguish the branch types as shown in
Table 4-49.
Table 4-49.
Opcode
Bits 40:37
The indirect return branch instructions encoded within major opcodes 0 use a 3-bit
opcode extension field in bits 8:6 (btype) to distinguish the branch types as shown in
Table 4-50.
Table 4-50.
Opcode
Bits 40:37
All of the branch instructions have a 1-bit sequential prefetch opcode hint extension
field, p, in bit 12.
Table 4-51.
The IP-relative and indirect branch instructions all have a 2-bit branch prediction
"whether" opcode hint extension field in bits 34:33 (wh) as shown in
Indirect call instructions have a 3-bit "whether" opcode hint extension field in bits
34:32 (wh) as shown in
Volume 3: Instruction Formats
Indirect Branch Types
x
6
Bits 32:27
0 20
Indirect Return Branch Types
x
6
Bits 32:27
0 21
Table 4-51 summarizes these assignments.
Sequential Prefetch Hint Completer
p
Bit 12
0
1
Table 4-53.
btype
Bits 8:6
0
1
2
3
4
5
6
7
btype
Bits 8:6
0
1
2
3
4
5
6
7
ph
.few
.many
br.cond B4
br.ia B4
e
e
e
e
e
e
e
e
e
e
br.ret B4
e
e
e
Table 4-52.
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