Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1199

Some processors may implement the Reserved if PR[qp] is 1 (purple) and Reserved if
PR[qp] is 1 B-unit (cyan) encodings in the L+X opcode space as Reserved (brown).
These encodings appear in the L+X column of
Table 4-69 on page
Table 4-72 on page
Reserved (brown), the operating system is required to provide an Illegal Operation fault
handler which emulates them as Reserved if PR[qp] is 1 (cyan/purple) by decoding the
reserved opcodes, checking the qualifying predicate, and returning to the next
instruction if PR[qp] is 0.
Constant 0 fields in instructions must be 0 or undefined operation results. The
undefined operation may include checking that the constant field is 0 and causing an
Illegal Operation fault if it is not. If an instruction having a constant 0 field also has a
qualifying predicate (qp field), the fault or other undefined operation must not occur if
PR[qp] is 0. For constant 0 fields in instruction bits 5:0 (normally used for qp), the fault
or other undefined operation may or may not depend on the PR addressed by those
bits.
Ignored (white space) fields in instructions should be coded as 0. Although ignored in
this revision of the architecture, future architecture revisions may define these fields as
hint extensions. These hint extensions will be defined such that the 0 value in each field
corresponds to the default hint. It is expected that assemblers will automatically set
these fields to zero by default.
Unused opcode hint extension values (white color entries in Hint Completer tables)
should not be used by software. Processors must perform the architected functional
behavior of the instruction independent of the hint extension value (whether defined or
unused), but different processor models may interpret unused opcode hint extension
values in different ways, resulting in undesirable performance effects.
4.2 A-Unit Instruction Encodings
4.2.1 Integer ALU
All integer ALU instructions are encoded within major opcode 8 using a 2-bit opcode
extension field in bits 35:34 (x
in bits 28:27 (x
reserved opcode extension field in bit 33 (v
v assignments,
e
Table 4-12 on page 3:306
also share major opcode 8).
Table 4-8.
Opcode
Bits
40:37
8
3:300
3:366, Table 4-70 on page
3:367. On processors which implement these encodings as
2a
), a 4-bit opcode extension field in bits 32:29 (x
2b
Table 4-9 shows the integer ALU 4-bit+2-bit assignments, and
shows the multimedia ALU 1-bit+2-bit assignments (which
Integer ALU 2-bit+1-bit Opcode Extensions
x
2a
Bits
35:34
0 Integer ALU 4-bit+2-bit Ext
1
2 adds – imm
3 addp4 – imm
Table 4-3 on page
3:366,
) and most have a second 2-bit opcode extension field
). Table 4-8
e
v
e
Bit 33
0
(Table 4-9)
Multimedia ALU 1-bit+2-bit Ext
A4
14
A4
14
3:295, and in
Table 4-71 on page 3:367, and
), and a 1-bit
4
shows the 2-bit x
2a
1
(Table 4-12)
Volume 3: Instruction Formats
and 1-bit