Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1497

FXCH—Exchange Register Contents
Opcode
D9 C8+i
D9 C9
Description
Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified,
the contents of ST(0) and ST(1) are exchanged.
This instruction provides a simple means of moving values in the FPU register stack to
the top of the stack [ST(0)], so that they can be operated on by those floating-point
instructions that can only operate on values in ST(0). For example, the following
instruction sequence takes the square root of the third register from the top of the
register stack:
FXCH ST(3);
FSQRT;
FXCH ST(3);
Operation
IF number-of-operands is 1
THEN
temp  ST(0);
ST(0)  SRC;
SRC  temp;
ELSE
temp  ST(0);
ST(0)  ST(1);
ST(1)  temp;
FI;
FPU Flags Affected
C1
C0, C2, C3
Floating-point Exceptions
#IS
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Protected Mode Exceptions
#NM
Volume 4: Base IA-32 Instruction Reference
Instruction Description
FXCH ST(i) Exchange the contents of ST(0) and ST( i )
FXCH Exchange the contents of ST(0) and ST(1)
Set to 0 if stack underflow occurred; otherwise, cleared to 0.
Undefined.
Stack underflow occurred.
Abort.
EM or TS in CR0 is set.
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