Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1651

SAL/SAR/SHL/SHR—Shift Instructions (Continued)
Description
Shift the bits in the first operand (destination operand) to the left or right by the
number of bits specified in the second operand (count operand). Bits shifted beyond the
destination operand boundary are first shifted into the CF flag, then discarded. At the
end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
The destination operand can be a register or a memory location. The count operand can
be an immediate value or register CL. The count is masked to 5 bits, which limits the
count range to from 0 to 31. A special opcode encoding is provide for a count of 1.
The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same
operation; they shift the bits in the destination operand to the left (toward more
significant bit locations). For each shift count, the most significant bit of the destination
operand is shifted into the CF flag, and the least significant bit is cleared.
The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of
the destination operand to the right (toward less significant bit locations). For each shift
count, the least significant bit of the destination operand is shifted into the CF flag, and
the most significant bit is either set or cleared depending on the instruction type. The
SHR instruction clears the most significant bit; the SAR instruction sets or clears the
most significant bit to correspond to the sign (most significant bit) of the original value
in the destination operand. In effect, the SAR instruction fills the empty bit position's
shifted value with the sign of the unshifted value.
The SAR and SHR instructions can be used to perform signed or unsigned division,
respectively, of the destination operand by powers of 2. For example, using the SAR
instruction shift a signed integer 1 bit to the right divides the value by 2.
Using the SAR instruction to perform a division operation does not produce the same
result as the IDIV instruction. The quotient from the IDIV instruction is rounded toward
zero, whereas the "quotient" of the SAR instruction is rounded toward negative infinity.
This difference is apparent only for negative numbers. For example, when the IDIV
instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR
instruction is used to shift -9 right by two bits, the result is -3 and the "remainder" is
+3; however, the SAR instruction stores only the most significant bit of the remainder
(in the CF flag).
The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is cleared to 0 if
the most-significant bit of the result is the same as the CF flag (that is, the top two bits
of the original operand were the same); otherwise, it is set to 1. For the SAR
instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag
is set to the most-significant bit of the original operand.
Operation
tempCOUNT  COUNT;
tempDEST  DEST;
WHILE (tempCOUNT
DO
Volume 4: Base IA-32 Instruction Reference
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