Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1175

xma
xma — Fixed-Point Multiply Add
( ) xma.l
Format: qp
( ) xma.lu
qp
( ) xma.h
qp
( ) xma.hu
qp
Two source operands (FR
Description:
and multiplied. The third source operand (FR
product. The upper or lower 64 bits of the resultant sum are selected and placed in FR
.
f
1
In the high_unsigned_form, the significand fields of FR
unsigned integers and multiplied to produce a full 128-bit unsigned result. The
significand field of FR
64-bits of the resultant sum are placed in the significand field of FR
In the high_form, the significand fields of FR
and multiplied to produce a full 128-bit signed result. The significand field of FR
zero extended and added to the product. The most significant 64-bits of the resultant
sum are placed in the significand field of FR
In the other forms, the significand fields of FR
and multiplied to produce a full 128-bit signed result. The significand field of FR
zero extended and added to the product. The least significant 64-bits of the resultant
sum are placed in the significand field of FR
In all forms, the exponent field of FR
(0x1003E) and the sign field of FR
Note: f1 as an operand is not an integer 1; it is just the register file format's 1.0
value.
In all forms, if any of FR
the computed result.
3:276
= ,
f f f f
1 3 4, 2
= ,
f f f f
1 3 4, 2
= ,
f f f f
1 3 4, 2
= ,
f f f f
1 3 4, 2
and FR
f
3
is zero extended and added to the product. The most significant
f
2
, FR , or FR
f f
3 4
pseudo-op of: (
) are treated as either signed or unsigned integers
f
4
) is zero extended and added to the
f
2
and FR
f
3
and FR are treated as signed integers
f f
3 4
.
f
1
and FR are treated as signed integers
f f
3 4
.
f
1
is set to the biased exponent for 2.0
f
1
is set to positive (0).
f
1
is a NaTVal, FR
f
2
low_form
) xma.l = , ,
qp f f f f
1 3 4 2
high_form
high_unsigned_form
are treated as
f
4
.
f
1
f
2
f
2
63
is set to NaTVal instead of
f
1
Volume 3: Instruction Reference
F2
F2
F2
is
is