Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1633

RDMSR—Read from Model Specific Register
Opcode
0F 32
Description
Loads the contents of a 64-bit model specific register (MSR) specified in the ECX
register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits
of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits
are implemented in the MSR being read, the values returned to EDX:EAX in
unimplemented bit locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) will be generated. Specifying a
reserved or unimplemented MSR address in ECX will also cause a general protection
exception.
The MSRs control functions for testability, execution tracing, performance-monitoring
and machine check errors.
The CPUID instruction should be used to determine whether MSRs are supported
(EDX[5]=1) before using this instruction.
See model-specific instructions for all the MSRs that can be written to with this
instruction and their addresses
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,RDMSR);
EDX:EAX  MSR[ECX];
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
Real Address Mode Exceptions
#GP
Volume 4: Base IA-32 Instruction Reference
Instruction Description
RDMSR Load MSR specified by ECX into EDX:EAX
Mandatory Instruction Intercept.
If the current privilege level is not 0.
If the value in ECX specifies a reserved or unimplemented MSR
address.
If the current privilege level is not 0
If the value in ECX specifies a reserved or unimplemented MSR
address.
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