Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1659

SETcc—Set Byte on Condition (Continued)
Many of the SETcc instruction opcodes have alternate mnemonics. For example, the
SETG (set byte if greater) and SETNLE (set if not less or equal) both have the same
opcode and test for the same condition: ZF equals 0 and SF equals OF. These alternate
mnemonics are provided to make code more intelligible.
Some languages represent a logical one as an integer with all bits set. This
representation can be arrived at by choosing the mutually exclusive condition for the
SETcc instruction, then decrementing the result. For example, to test for overflow, use
the SETNO instruction, then decrement the result.
Operation
IF condition
THEN DEST  1
ELSE DEST  0;
FI;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
Volume 4: Base IA-32 Instruction Reference
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
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