Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1374

CMPS/CMPSB/CMPSW/CMPSD—Compare String Operands (Continued)
Operation
temp SRC1  SRC2;
SetStatusFlags(temp);
IF (byte comparison)
THEN IF DF = 0
THEN (E)DI  1; (E)SI  1;
ELSE (E)DI  -1; (E)SI  -1;
FI;
ELSE IF (word comparison)
THEN IF DF = 0
FI;
ELSE (* doubleword comparison *)
FI;
FI;
Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result of the
comparison.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#GP
#SS
4:72
THEN DI  2; (E)SI  2;
ELSE DI  -2; (E)SI  -2;
THEN IF DF = 0
THEN EDI  4; (E)SI  4;
ELSE EDI  -4; (E)SI  -4;
FI;
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
Volume 4: Base IA-32 Instruction Reference