Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1896
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INDEX
SIDT Instruction 4:359
Single Step Trap 2:151
SLDT Instruction 4:367
SMSW Instruction 4:369
Software Pipelining 1:19, 1:75, 1:145, 1:181
Speculation 1:16, 1:142, 1:151
Control Speculation 1:16
Data Speculation 1:17
Recovery Code 1:17, 2:580
Speculation Check 1:156
SQRTPS Instruction 4:551
SQRTSS Instruction 4:552
srlz Instruction 3:249
SSE Instructions 4:463
ssm Instruction 3:250
st Instruction 3:251
Stacked Calling Convention 2:352
Stacked General Registers 2:550
Stacked Registers 1:144
Static Calling Convention 2:352
Static General Registers 2:550
STC Instruction 4:371
STD Instruction 4:372
stf Instruction 3:254
STI Instruction 4:373
STMXCSR Instruction 4:553
Stops 1:38
Store Instructions 1:59
Stores to Memory 1:147
STOS Instruction 4:376
STOSB Instruction 4:376
STOSD Instruction 4:376
STOSW Instruction 4:376
STR Instruction 4:378
SUB Instruction 4:379
sub Instruction 3:256
SUBPS Instruction 4:554
SUBSS Instruction 4:555
sum Instruction 3:257
sxt Instruction 3:258
sync Instruction 3:259
sync.i 2:526
System Abstraction Layer - See SAL (System
Abstraction Layer)
System Architecture 1:20
System Environment 2:13
System Programmer's Guide 2:501
System State 2:20
T
tak Instruction 3:260
Taken Branch trap 2:151
Task Priority Register (TPR) 2:123, 2:605
tbit Instruction 3:261
TC (Translation Cache) 2:49, 2:567
Index:10
Template Field Encoding 1:38
Templates 1:141
TEST Instruction 4:381
tf Instruction 3:263
thash Instruction 3:265
TLB (Translation Lookaside Buffer) 2:47, 2:565
tnat Instruction 3:266
tpa Instruction 3:268
TPR (Task Priority Register) 2:123, 2:605
TR (Translation Register) 2:48, 2:566
Translation Cache (TC) 2:49, 2:567
purge 2:568
Translation Instructions 2:60
Translation Lookaside Buffer (TLB) 2:47, 2:565
Translation Register (TR) 2:48, 2:566
Traps 2:96, 2:537
ttag Instruction 3:269
U
UCOMISS Instruction 4:556
UD2 Instruction 4:383
UEFI (Unified Extensible Firmware Interface)
2:630
UM (User Mask Register) 1:33
UNAT (User NaT Collection Register) 1:31, 1:156
Uncacheable Page 2:77
Unchanged Register 2:352
Unordered Semantics 2:507
unpack Instruction 3:270
UNPCKHPS Instruction 4:558
UNPCKLPS Instruction 4:560
User Mask (UM) 1:33
User NaT Collection Register (UNAT) 1:31, 1:156
V
VERR Instruction 4:384
VERW Instruction 4:384
VHPT (Virtual Hash Page Table) 2:61, 2:571
VHPT Translation Vector 2:173
Virtual Addressing 2:45
Virtual Hash Page Table (VHPT) 2:61, 2:571
Virtual Machine Monitor (VMM) 2:352
Virtual Processor Descriptor (VPD) 2:325, 2:352
Virtual Processor State 2:352
Virtual Processor Status Register (VPSR) 2:327
Virtual Region Number (VRN) 2:561
Virtualization 2:44, 2:324
Virtualization Acceleration Control (vac) 2:329
Virtualization Disable Control (vdc) 2:329
VMM (Virtual Machine Monitor) 2:352
vmsw Instruction 3:273
VPD (Virtual Processor Descriptor) 2:325, 2:352
VPSR (Virtual Processor Status Register) 2:327
VRN (Virtual Region Number) 2:561
Index for Volumes 1, 2, 3 and 4
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