Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1855

STMXCSR: Store SSE Control/Status
Opcode
0F,AE,/3
Operation: m32 = MXCSR;
The MXCSR control/status register is used to enable masked/unmasked exception
Description:
handling, to set rounding modes, to set flush-to-zero mode, and to view exception
status flags. Refer to LDMXCSR for a description of the format of MXCSR. The linear
address corresponds to the address of the least-significant byte of the referenced
memory data. The reserved bits in the MXCSR are stored as zeroes.
None.
FP Exceptions:
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if
CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault. #AC for
unaligned memory reference.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
The usage of Repeat (F2H, F3H) and Operand Size (66H) prefixes with STMXCSR is
Comments:
reserved. Different processor implementations may handle this prefix differently. Usage
of this prefix with STMXCSR risks incompatibility with future processors.
Volume 4: IA-32 SSE Instruction Reference
Instruction
STMXCSR m32
NaT Register Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
Store SSE control/status word to m32.
4:553