Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1146
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shr — Shift Right
(
) shr
Format:
qp
r
1
(
) shr.u
qp
(
) shr
qp
r
1
(
) shr.u
qp
The value in GR
Description:
vacated bit positions are filled with bit 63 of GR r
bit positions are filled with zeroes. The number of bit positions to shift is specified by
the value in GR
unsigned number. If the value in GR r
(for the unsigned_form, or if bit 63 of GR r
bit 63 of GR r
If the .u completer is specified, the shift is unsigned (logical), otherwise it is signed
(arithmetic).
See
"extr — Extract" on page 3:54
Operation:
if (PR[qp]) {
check_target_register(r
if (signed_form) {
count = (GR[r
GR[r
} else {
count = GR[r
GR[r
}
GR[r
].nat = GR[r
1
}
Illegal Operation fault
Interruptions:
Volume 3: Instruction Reference
=
,
r
r
3
2
=
,
r
r
r
1
3
2
=
, count
r
3
6
=
, count
r
r
1
3
6
is shifted to the right and placed in GR r
r
3
or by an immediate value count
r
2
was 1).
3
);
1
] > 63) ? 63 : GR[r
2
] = shift_right_signed(GR[r
1
];
2
] = (count > 63) ? 0 : shift_right_unsigned(GR[r
1
].nat || GR[r
2
pseudo-op of: (
) extr
qp
pseudo-op of: (
) extr.u
qp
; in the unsigned_form the vacated
3
. The shift count is interpreted as an
6
is greater than 63, then the result is all zeroes
2
was 0) or all ones (for the signed_form if
3
for the immediate forms.
];
2
], count);
3
].nat;
3
signed_form
unsigned_form
=
, count
, 64-count
r
r
1
3
6
6
=
, count
, 64-count
r
r
1
3
6
6
. In the signed_form the
1
], count);
3
shr
I5
I5
3:247
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