Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1866

PAVGB/PAVGW: Packed Average (Continued)
temp[i] = zero_ext(x[i], 16) + zero_ext(y[i], 16);
res[i] = (temp[i] +1) >> 1;
}
mm1[15-0]
...
mm1[63-48]
}
The PAVG instructions add the unsigned data elements of the source operand to the
Description:
unsigned data elements of the destination register, along with a carry-in. The results of
the add are then each independently right shifted by one bit position. The high order
bits of each element are filled with the carry bits of the corresponding sum.
The destination operand is a MMX technology register. The source operand can either
be a MMX technology register or a 64-bit memory operand.
The PAVGB instruction operates on packed unsigned bytes and the PAVGW instruction
operates on packed unsigned words.
None.
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #MF if there is a pending FPU
exception; #AC for unaligned memory reference. To enable #AC exceptions, three
conditions must be true(CR0.AM is set; EFLAGS.AC is set; current CPL is 3).
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #MF if there is a
pending FPU exception.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault; #AC for
unaligned memory references (if the current privilege level is 3).
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
4:564
= res[0];
= res[3];
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault
Volume 4: IA-32 SSE Instruction Reference