Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1662

SGDT/SIDT—Store Global/Interrupt Descriptor Table Register (Continued)
Protected Mode Exceptions
#UD
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Real Address Mode Exceptions
#UD
#GP
#SS
Virtual 8086 Mode Exceptions
#UD
#GP(0)
#SS(0)
#PF(fault-code)
#AC(0)
Intel Architecture Compatibility
The 16-bit forms of the SGDT and SIDT instructions are compatible with the Intel 286
processor, if the upper 8 bits are not referenced. The Intel 286 processor fills these bits
with 1s; the Pentium Pro processor fills these bits with 0s.
4:360
If the destination operand is a register.
If the destination is located in a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it
contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If an unaligned memory access occurs when the CPL is 3 and
alignment checking is enabled.
If the destination operand is a register.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If the destination operand is a register.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If a memory operand effective address is outside the SS segment
limit.
If a page fault occurs.
If an unaligned memory access occurs when alignment checking is
enabled.
Volume 4: Base IA-32 Instruction Reference