Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1880

MOVNTPS: Move Aligned Four Packed Single-FP Non-temporal
Opcode
0F,2B, /r
Operation: m128 = xmm;
The linear address corresponds to the address of the least-significant byte of the
Description:
referenced memory data. This store instruction minimizes cache pollution.
General protection exception if not aligned on 16-byte boundary, regardless of
FP Exceptions:
segment.
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if CRCR4.OSFXSR(bit 9) =
0; #UD if CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Itanium Mem Faults VHPT Data Fault, Data TLB Fault, Alternate Data TLB Fault, Data
MOVTNPS should be used when dealing with 16-byte aligned single-precision FP
Comments:
numbers. MOVNTPS minimizes pollution in the cache hierarchy. As a consequence of
the resulting weakly-ordered memory consistency model, a fencing operation should be
used if multiple processors may use different memory types to read/write the memory
location. See Section 4.6.1.9, "Cacheability Control Instructions" for further information
about non-temporal stores.
The usage of Repeat Prefixes(F2H, F3H) with MOVNTPS is reserved. Different processor
implementations may handle this prefix differently. Usage of this prefix with MOVNTPS
risks incompatibility with future processors.
4:578
Instruction
MOVNTPS m128, xmm
Disabled FP Register Fault if PSR.dfl is 1, NaT Register
Consumption Fault
Page Not Present Fault, Data NaT Page Consumption Abort, Data
Key Miss Fault, Data Key Permission Fault, Data Access Rights
Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
Move 128 bits representing four packed SP FP data from XMM
register to Mem, minimizing pollution in the cache hierarchy.
Volume 4: IA-32 SSE Instruction Reference