Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1331

AND—Logical AND
Opcode
24 ib
25 iw
25 id
80 /4 ib
81 /4 iw
81 /4 id
83 /4 ib
83 /4 ib
20 /r
21 / r
21 / r
22 / r
23 / r
23 / r
Description
Performs a bitwise AND operation on the destination (first) and source (second)
operands and stores the result in the destination operand location. The source operand
can be an immediate, a register, or a memory location; the destination operand can be
a register or a memory location.
Operation
DEST  DEST AND SRC;
Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result.
The state of the AF flag is undefined.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
Protected Mode Exceptions
#GP(0)
#SS(0)
Volume 4: Base IA-32 Instruction Reference
Instruction
AND AL, imm8
AND AX, imm16
AND EAX, imm32
AND r/m8,imm8
AND r/m16,imm16
AND r/m32,imm32
AND r/m16,imm8
AND r/m32,imm8
AND r/m8,r8
AND r/m16,r16
AND r/m32,r32
AND r8,r/m8
AND r16,r/m16
AND r32,r/m32
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
If the destination operand points to a nonwritable segment.
If a memory operand effective address is outside the CS, DS, ES, FS,
or GS segment limit.
If the DS, ES, FS, or GS register contains a null segment selector.
If a memory operand effective address is outside the SS segment
limit.
Description
AL AND imm8
AX AND i mm16
EAX AND imm32
r/m8 AND imm8
r/m16 AND imm16
r/m32 AND imm32
r/m16 AND imm8
r/m32 AND imm8
r/m8 AND r8
r/m16 AND r16
r/m32 AND r32
r8 AND r/m8
r16 AND r/m16
r32 AND r/m32
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