Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1227

Table 4-38.
Opcode
Bits
40:37
6
The load and store instructions all have a 2-bit cache locality opcode hint extension field
in bits 29:28 (hint).
Table 4-39. Load Hint Completer
hint
Bits 29:28
0
1
2
3
Table 4-40. Store Hint Completer
hint
Bits 29:28
0
1
2
3
3:328
Floating-point Load Pair +Imm Opcode Extensions
m x
Bit Bit
Bits
36 27
35:32
0
0
1
2
3
4
5
6
7
1 1
8
9
A
B
C
D
E
F
Table 4-39
ldhint
none
.nt1
.nta
sthint
none
.nta
x
6
Bits 31:30
1
ldfp8 M12
ldfp8.s M12
ldfp8.a M12
ldfp8.sa M12
ldfp8.c.clr M12
ldfp8.c.nc M12
and Table 4-40 summarize these assignments.
2 3
ldfps M12 ldfpd
ldfps.s M12 ldfpd.s
ldfps.a M12 ldfpd.a
ldfps.sa M12 ldfpd.sa
ldfps.c.clr M12 ldfpd.c.clr
ldfps.c.nc M12 ldfpd.c.nc
Volume 3: Instruction Formats
M12
M12
M12
M12
M12
M12