Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1691

WRMSR—Write to Model Specific Register
Opcode
0F 30
Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR)
specified in the ECX register. The high-order 32 bits are copied from EDX and the
low-order 32 bits are copied from EAX. Always set undefined or reserved bits in an MSR
to the values previously read.
This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) will be generated. Specifying a
reserved or unimplemented MSR address in ECX will also cause a general protection
exception.
When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated,
including the global entries see the Intel Architecture Software Developer's Manual,
Volume 3).
The MSRs control functions for testability, execution tracing, performance-monitoring
and machine check errors. See model-specific instructions for all the MSRs that can be
written to with this instruction and their addresses.
The WRMSR instruction is a serializing instruction.
The CPUID instruction should be used to determine whether MSRs are supported
(EDX[5]=1) before using this instruction.
Operation
IF Itanium System Environment THEN IA-32_Intercept(INST,WRMSR);
MSR[ECX]  EDX:EAX;
Flags Affected
None.
Additional Itanium System Environment Exceptions
IA-32_Intercept
Protected Mode Exceptions
#GP(0)
Real Address Mode Exceptions
#GP
Volume 4: Base IA-32 Instruction Reference
Instruction Description
WRMSR Write the value in EDX:EAX to MSR specified by ECX
Mandatory Instruction Intercept.
If the current privilege level is not 0.
If the value in ECX specifies a reserved or unimplemented MSR
address.
If the current privilege level is not 0
If the value in ECX specifies a reserved or unimplemented MSR
address.
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