Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1132
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ptc.l — Purge Local Translation Cache
(
) ptc.l
Format:
qp
r
The instruction and data translation cache of the local processor is searched for all
Description:
entries whose virtual address and page size partially or completely overlap the specified
purge virtual address and purge address range. All these entries are removed.
The purge virtual address is specified by GR
identifier is selected by GR
purge as 1<<GR[
for details on supported page sizes for TLB purges.
The processor ensures that all entries matching the purging parameters are removed.
However, based on the processor model, the translation cache may be also purged of
more translations than specified by the purge parameters up to and including removal
of all entries within the translation cache.
This instruction can only be executed at the most privileged level, and when PSR.vm is
0.
This is a local operation, no purge broadcast to other processors occurs in a
multiprocessor system. This instruction ensures that all prior stores are made locally
visible before the actual purge operation is performed.
Operation:
if (PR[qp]) {
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (GR[r
register_nat_consumption_fault(0);
if (unimplemented_virtual_address(GR[r
unimplemented_data_address_fault(0);
if (PSR.vm == 1)
virtualization_fault();
tmp_rid = RR[GR[r
tmp_va = GR[r
tmp_size = GR[r
tmp_va = align_to_size_boundary(tmp_va, tmp_size);
tlb_must_purge_dtc_entries(tmp_rid, tmp_va, tmp_size);
tlb_must_purge_itc_entries(tmp_rid, tmp_va, tmp_size);
}
Machine Check abort
Interruptions:
Privileged Operation fault
Register NaT Consumption fault
Software must issue the appropriate data and/or instruction serialization operation to
Serialization:
ensure the purge is completed before a data access, non-access reference, or
instruction fetch access dependent upon the purge.
Volume 3: Instruction Reference
,
r
3
2
bits {63:61}. GR
r
3
]{7:2} bytes in size. See
r
2
].nat || GR[r
].nat)
3
2
]{63:61}].rid;
3
]{60:0};
3
]{7:2};
2
bits{60:0} and the purge region
r
3
specifies the address range of the
r
2
Section 4.1.1.7, "Page Sizes" on page 2:57
], PSR.vm))
3
Unimplemented Data Address fault
Virtualization fault
ptc.l
M45
3:233
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