Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1236
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4.4.1.12
Floating-point Load Pair – Increment by Immediate
40
M12
Instruction
ldfps. ldhint
ldfpd. ldhint
ldfp8. ldhint
ldfps.s. ldhint
ldfpd.s. ldhint
ldfp8.s. ldhint
ldfps.a. ldhint
ldfpd.a. ldhint
ldfp8.a. ldhint
ldfps.sa. ldhint
ldfpd.sa. ldhint
ldfp8.sa. ldhint
ldfps.c.clr. ldhint
ldfpd.c.clr. ldhint
ldfp8.c.clr. ldhint
ldfps.c.nc. ldhint
ldfpd.c.nc. ldhint
ldfp8.c.nc. ldhint
4.4.2
Line Prefetch
The line prefetch instructions are encoded in major opcodes 6 and 7 along with the
floating-point load/store instructions. See
summary of the opcode extensions.
The line prefetch instructions all have a 2-bit cache locality opcode hint extension field
in bits 29:28 (hint) as shown in
Table 4-41. Line Prefetch Hint Completer
hint
Bits 29:28
0
1
2
3
Volume 3: Instruction Formats
37 36 35
30 29 28 27 26
6
m
x
hint x
6
4
1
6
2
Operands
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
f
, f
= [ r
], 8
1
2
3
f
, f
= [ r
], 16
1
2
3
lfhint
none
.nt1
.nt2
.nta
20 19
r
f
3
2
1
7
7
Opcode
m
6
1
"Loads and Stores" on page 3:323
Table
4-44.
13 12
6 5
f
1
7
Extension
x
x
hint
6
02
03
01
06
07
05
0A
0B
09
See Table 4-39
1
on page 3:328
0E
0F
0D
22
23
21
26
27
25
for a
0
qp
6
3:337
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