Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1149

ssm
ssm — Set System Mask
( ) ssm
Format: qp imm
The
Description: imm
24
in the system mask. See
page 2:23.
The PSR system mask can only be written at the most privileged level, and when
PSR.vm is 0.
The contents of the interruption resources (that are overwritten when the PSR.ic bit is
1), are undefined if an interruption occurs between the enabling of the PSR.ic bit and a
subsequent instruction serialize operation.
Operation:
if (PR[qp]) {
if (PSR.cpl != 0)
privileged_operation_fault(0);
if (is_reserved_field(PSR_TYPE, PSR_SM, imm
reserved_register_field_fault();
if (PSR.vm == 1)
virtualization_fault();
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
if (imm
}
Privileged Operation fault
Interruptions:
Reserved Register/Field fault
Software must issue a data serialize or instruction serialize operation before issuing
Serialization:
instructions dependent upon the altered PSR bits from the ssm instruction. Unlike with
the rsm instruction, setting the PSR.i bit is not treated specially. Refer to
"Serialization" on page 2:17
3:250
24
operand is ORed with the system mask (PSR{23:0}) and the result is placed
Section 3.3.2, "Processor Status Register (PSR)" on
{1}) PSR{1} = 1;)
24
{2}) PSR{2} = 1;)
24
{3}) PSR{3} = 1;)
24
{4}) PSR{4} = 1;)
24
{5}) PSR{5} = 1;)
24
{13}) PSR{13} = 1;)
24
{14}) PSR{14} = 1;)
24
{15}) PSR{15} = 1;)
24
{17}) PSR{17} = 1;)
24
{18}) PSR{18} = 1;)
24
{19}) PSR{19} = 1;)
24
{20}) PSR{20} = 1;)
24
{21}) PSR{21} = 1;)
24
{22}) PSR{22} = 1;)
24
{23}) PSR{23} = 1;)
24
for a description of serialization.
))
24
// be
// up
// ac
// mfl
// mfh
// ic
// i
// pk
// dt
// dfl
// dfh
// sp
// pp
// di
// si
Virtualization fault
Volume 3: Instruction Reference
M44
Section 3.2,