Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1410

FCHS—Change Sign
Opcode
D9 E0
Description
Complements the sign bit of ST(0). This operation changes a positive value into a
negative value of equal magnitude or vice-versa. The following table shows the results
obtained when creating the absolute value of various classes of numbers.
ST(0) SRC
 •
 F
 0
 0
+F
+ 
NaN
Note:
Fmeans finite-real number.
Operation
SignBit(ST(0))  NOT (SignBit(ST(0)))
FPU Flags Affected
C1
C0, C2, C3
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Floating-point Exceptions
#IS
Protected Mode Exceptions
#NM
Real Address Mode Exceptions
#NM
Virtual 8086 Mode Exceptions
#NM
4:108
Instruction Description
FCHS Complements sign of ST(0)
ST(0) DEST
+ 
+F
 0
 0
 F
 •
NaN
Set to 0 if stack underflow occurred; otherwise, cleared to 0.
Undefined.
Abort.
Stack underflow occurred.
EM or TS in CR0 is set.
EM or TS in CR0 is set.
EM or TS in CR0 is set.
Volume 4: Base IA-32 Instruction Reference