Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1240
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4.4.5.3
Integer Advanced Load Check
40
M22
Instruction
chk.a.nc
chk.a.clr
4.4.5.4
Floating-point Advanced Load Check
40
M23
Instruction
chk.a.nc
chk.a.clr
4.4.6
Cache/Synchronization/RSE/ALAT
The cache/synchronization/RSE/ALAT instructions are encoded in major opcode 0 along
with the memory management instructions. See
page 3:345
4.4.6.1
Sync/Fence/Serialize/ALAT Control
40
M24
invala
fwb
mf
mf.a
srlz.d
srlz.i
sync.i
Volume 3: Instruction Formats
37 36 35
33 32
0
s
x
3
4
1
3
Operands
r
, target
1
25
37 36 35
33 32
0
s
x
3
4
1
3
Operands
f
, target
1
25
for a summary of the opcode extensions.
37 36 35
33 32 31 30
0
x
x
x
3
2
4
4
1
3
2
4
Instruction
imm
20b
20
Opcode
0
imm
20b
20
Opcode
0
"System/Memory Management" on
27 26
21
Opcode
x
3
0
0
13 12
6 5
r
qp
1
7
Extension
x
3
4
5
13 12
6 5
f
qp
1
7
Extension
x
3
6
7
6 5
qp
Extension
x
x
4
2
0
1
0
2
2
3
0
1
3
3
0
6
0
6
0
6
3:341
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