Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1258
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4.6.1.1
Floating-point Multiply Add
40
F1
Instruction
fma. sf
fma.s. sf
fma.d. sf
fpma. sf
fms. sf
fms.s. sf
fms.d. sf
fpms. sf
fnma. sf
fnma.s. sf
fnma.d. sf
fpnma. sf
4.6.1.2
Fixed-point Multiply Add
40
F2
Instruction
xma.l
xma.h
xma.hu
4.6.2
Parallel Floating-point Select
40
F3
Instruction
fselect
4.6.3
Compare and Classify
The predicate setting floating-point compare instructions are encoded within major
opcode 4 using three 1-bit opcode extension fields in bits 33 (r
and a 2-bit opcode extension field (sf) in bits 35:34. The opcode, r
assignments are shown in
page
3:358.
The parallel floating-point compare instructions are described on
Volume 3: Instruction Formats
37 36 35 34 33
8 - D
x sf
f
4
4
1
2
7
Operands
f
= f
, f
, f
1
3
4
2
37 36 35 34 33
E
x x
f
2
4
4
1
2
7
Operands
f
= f
, f
, f
1
3
4
37 36 35 34 33
E
x
f
4
4
1
2
7
Operands
f
= f
, f
, f
1
3
4
2
Table
27 26
20 19
f
f
3
7
7
Opcode
8
9
A
B
C
D
27 26
20 19
f
f
3
7
7
Opcode
E
2
27 26
20 19
f
f
3
7
7
Opcode
E
4-66. The sf assignments are shown in
13 12
6 5
f
2
1
7
Extension
x
sf
0
1
0
1
0
1
See Table 4-63 on
page 3:358
0
1
0
1
0
1
13 12
6 5
f
2
1
7
Extension
x
x
0
1
3
2
13 12
6 5
f
2
1
7
Extension
x
0
), 36 (r
), and 12 (t
a
b
, r
, and t
a
b
Table 4-63 on
page
3:362.
0
qp
6
0
qp
6
2
0
qp
6
),
a
a
3:359
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