Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1341

BSWAP—Byte Swap
Opcode
0F C8+ rd
Description
Reverses the byte order of a 32-bit (destination) register: bits 0 through 7 are swapped
with bits 24 through 31, and bits 8 through 15 are swapped with bits 16 through 23.
This instruction is provided for converting little-endian values to big-endian format and
vice versa.
To swap bytes in a word value (16-bit register), use the XCHG instruction. When the
BSWAP instruction references a 16-bit register, the result is undefined.
Operation
TEMP  DEST
DEST(7..0)  TEMP(31..24)
DEST(15..8)  TEMP(23..16)
DEST(23..16)  TEMP(15..8)
DEST(31..24)  TEMP(7..0)
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults NaT Register Consumption Abort.
Exceptions (All Operating Modes)
None.
Intel Architecture Compatibility Information
The BSWAP instruction is not supported on Intel architecture processors earlier than
the Intel486™ processor family. For compatibility with this instruction, include
functionally-equivalent code for execution on Intel processors earlier than the Intel486
processor family.
Volume 4: Base IA-32 Instruction Reference
Instruction Description
BSWAP r32 Reverses the byte order of a 32-bit register.
4:39