Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1834

MOVLHPS: Move Low to High Packed Single-FP
Opcode
0F,16,/r
Operation: // move instruction
xmm1[127-64] = xmm2[63-0];
xmm1[63-0] = xmm1[63-0];
The lower 64-bits of the source register xmm2 are loaded into the upper 64-bits of the
Description:
128-bit register xmm1 and the lower 64-bits of xmm1 are left unchanged.
None
FP Exceptions:
None
Numeric Exceptions:
Protected Mode Exceptions:
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if CRCR4.OSFXSR(bit 9) = 0; #UD
if CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
#UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if CRCR4.OSFXSR(bit 9) = 0; #UD
if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode.
Additional Itanium System Environment Exceptions
Itanium Reg Faults
Comments:
The usage of Repeat (F2H, F3H) and Operand Size (66H) prefixes with MOVLHPS is
Example:
reserved. Different processor implementations may handle these prefixes differently.
Usage of these prefixes with MOVLHPS risks incompatibility with future processors.
4:532
Instruction
MOVLHPS xmm1, xmm2
Disabled FP Register Fault if PSR.dfl is 1
Description
Move 64 bits representing lower two SP operands from XMM2
to upper two fields of XMM1 register.
Volume 4: IA-32 SSE Instruction Reference