Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1222

4.3.9 Test Feature
40
I30
Instruction
tf.z
tf.z.unc
tf.z.and
tf.nz.and
tf.z.or
tf.nz.or
tf.z.or.andcm
tf.nz.or.andcm
4.4 M-Unit Instruction Encodings
4.4.1 Loads and Stores
All load and store instructions are encoded within major opcodes 4, 5, 6, and 7 using a
6-bit opcode extension field in bits 35:30 (x
load/store, semaphores, and get FR) use two 1-bit opcode extension fields in bit 36 (m)
and bit 27 (x) as shown in
load/store, load pair, and set FR) use two 1-bit opcode extension fields in bit 36 (m)
and bit 27 (x) as shown in
Table 4-28.
Opcode
Bits 40:37
Table 4-29.
Opcode
Bits 40:37
The integer load/store opcode extensions are summarized in
Table 4-31 on page
FR opcode extensions in
Volume 3: Instruction Formats
37 36 35 34 33 32
5 t x t p
b 2 a 2
4 1 2 1 6
Operands
p , p = imm
1 2 5
Table
Table
Integer Load/Store/Semaphore/Get FR 1-bit Opcode
Extensions
m
Bit 36
0
0
4
1
1
Floating-point Load/Store/Load Pair/Set FR 1-bit Opcode
Extensions
m
Bit 36
0
0
6
1
1
3:324, and
Table 4-33 on page
27 26 20 19 18
0 x imm
7 1 5
Opcode
x t
2 a
0
5 0
1
). Instructions in major opcode 4 (integer
6
4-28. Instructions in major opcode 6 (floating-point
4-29.
x
Bit 27
0
1
0
1
x
Bit 27
0
1 FP Load Pair/set FR
0
1 FP Load Pair +Imm
Table 4-32 on page 3:325, and the semaphore and get
3:325. The floating-point load/store
14 13 12 11 6 5
y c p
5b 1
1 1 6
Extension
t y x
b
0
1
1 1
0
1
Load/Store (Table 4-30)
Semaphore/get FR (Table 4-33)
Load +Reg (Table 4-31)
FP Load/Store (Table 4-34)
(Table 4-37)
FP Load +Reg (Table 4-35)
(Table 4-38)
Table 4-30 on page
0
qp
6
c
0
1
0
1
0
1
0
1
3:324,
3:323