Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1721

PAND—Logical AND
Opcode
0F DB /r
Description
Performs a bitwise logical AND operation on the quadword source (second) and
destination (first) operands and stores the result in the destination operand location
(see Figure
memory location; the destination operand must be an MMX technology register. Each
bit of the result of the PAND instruction is set to 1 if the corresponding bits of the
operands are both 1; otherwise it is made zero
Figure 3-8.
mm
mm/m64
mm
Operation
DEST  DEST AND SRC;
Flags Affected
None.
Additional Itanium System Environment Exceptions
Itanium Reg Faults Disabled FP Register Fault if PSR.dfl is 1, NaT Register Consumption
Itanium Mem FaultsVHPT Data Fault, Nested TLB Fault, Data TLB Fault, Alternate Data
®
Volume 4: IA-32 Intel MMX™ Technology Instruction Reference
Instruction
PAND mm, mm/m64
3-8). The source operand can be an MMX technology register or a quadword
Operation of the PAND Instruction
PAND mm, mm/m64
1111111111111000000000000000010110110101100010000111011101110111
0001000011011001010100000011000100011110111011110001010110010101
0001000011011000000000000000000100010100100010000001010100010101
Abort.
TLB Fault, Data Page Not Present Fault, Data NaT Page Consumption
Abort, Data Key Miss Fault, Data Key Permission Fault, Data Access
Rights Fault, Data Access Bit Fault, Data Dirty Bit Fault
Description
AND quadword from mm/m64 to quadword in mm.
&
3006019
4:419