Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1215

4.3.2.2 Extract
40
I11
Instruction
extr.u
extr
4.3.2.3 Zero and Deposit
40
I12
Instruction
dep.z
4.3.2.4 Zero and Deposit Immediate
40
I13
Instruction
dep.z
4.3.2.5 Deposit Immediate
40
I14
Instruction
dep
4.3.2.6 Deposit
40
I15
Instruction
dep
4.3.3 Test Bit
All test bit instructions are encoded within major opcode 5 using a 2-bit opcode
extension field in bits 35:34 (x
36 (t ), 12 (c), 13 (y) and 19 (x).
b
3:316
37 36 35 34 33 32
5 x x len
2 6d
4 1 2 1 6
Operands
r = r , pos , len
1 3 6 6
37 36 35 34 33 32 27 26 25
5 x x len
2 6d
4 1 2 1 6
Operands
r = r , pos , len
1 2 6 6
37 36 35 34 33 32 27 26 25
5 s x x len
2 6d
4 1 2 1 6
Operands
r = imm , pos , len
1 8 6
1
37 36 35 34 33 32 27 26
5 s x x len
2 6d
4 1 2 1 6
Operands
r = imm , r , pos
1 1 3
37 36 31 30 27 26
4 cpos len
6d 4d
4 6 4
r = r , r
1 2 3
) plus five 1-bit opcode extension fields in bits 33 (t
2
27 26 20 19
r pos
3
7 6
Opcode
5
20 19
y cpos r
6c 2
1 6 7
Opcode
5
8
20 19
y cpos imm
6c 7b
1 6 7
Opcode
5
6
20 19
r cpos
3 6b
7 6
Opcode
, len
6 6
20 19
r r
3 2
7 7
Operands
, pos , len
6 4
Table 4-23 summarizes these assignments.
14 13 12 6 5
y r
6b 1
1 7
Extension
x x y
2
0
1 0
1
13 12 6 5
r
1
7
Extension
x x y
2
1 1 0
13 12 6 5
r
1
7
Extension
x x y
2
1 1 1
14 13 12 6 5
r
1
1 7
Extension
x x
2
5 3 1
13 12 6 5
r
1
7
Opcode
4
Volume 3: Instruction Formats
0
qp
6
0
qp
6
0
qp
6
0
qp
6
0
qp
6
),
a