Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1819

LDMXCSR: Load SSE Control/Status (Continued)
Bit 15 (FZ) is used to turn on the Flush To Zero mode (bit is set). Turning on the Flush
To Zero mode has the following effects during underflow situations:
• Zero results are returned with the sign of the true result.
• Precision and underflow exception flags are set.
The IEEE mandated masked response to underflow is to deliver the denormalized result
(i.e. gradual underflow); consequently, the flush to zero mode is not compatible with
IEEE Std. 754. It is provided primarily for performance reasons. At the cost of a slight
precision loss, faster execution can be achieved for applications where underflows are
common. Unmasking the underflow exception takes precedence over Flush To Zero
mode; this means that an exception handler will be invoked for a SSE instruction that
generates an underflow condition while this exception is unmasked, regardless of
whether flush to zero is enabled.
The other bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared;
attempting to write a non-zero value to these bits, using either the FXRSTOR or
LDMXCSR instructions, will result in a general protection exception.
The linear address corresponds to the address of the least-significant byte of the
referenced memory data.
General protection fault if reserved bits are loaded with non-zero values.
FP Exceptions:
None
Numeric Exceptions:
Protected Mode Exceptions:
#GP(0) for an illegal memory operand effective address in the CS, DS, ES, FS or GS
segments; #SS(0) for an illegal address in the SS segment; #PF(fault-code) for a page
fault; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set. #AC for unaligned memory
reference. To enable #AC exceptions, three conditions must be true(CR0.AM is set;
EFLAGS.AC is set; current CPL is 3); #UD if CRCR4.OSFXSR(bit 9) = 0; #UD if
CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions:
Interrupt 13 if any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH; #UD if CR0.EM = 1; #NM if TS bit in CR0 is set; #UD if
CRCR4.OSFXSR(bit 9) = 0; #UD if CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions:
Same exceptions as in Real Address Mode; #PF(fault-code) for a page fault. #AC for
unaligned memory reference.
Volume 4: IA-32 SSE Instruction Reference 4:517