Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1124
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Operation:
if (PR[qp]) {
check_target_register(r
shift_count = (variable_form ? GR[r
tmp_nat = (variable_form ? GR[r
if (two_byte_form) {
if (shift_count u> 16)
if (unsigned_form) {
} else {
}
} else {
if (shift_count > 32)
if (unsigned_form) {
} else {
}
}
GR[r
].nat = GR[r
1
}
Illegal Operation fault
Interruptions:
Volume 3: Instruction Reference
);
1
shift_count = 16;
GR[r
]{15:0}
= shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{31:16} = shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{47:32} = shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{63:48} = shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{15:0}
= shift_right_signed(sign_ext(GR[r
1
GR[r
]{31:16} = shift_right_signed(sign_ext(GR[r
1
GR[r
]{47:32} = shift_right_signed(sign_ext(GR[r
1
GR[r
]{63:48} = shift_right_signed(sign_ext(GR[r
1
shift_count = 32;
GR[r
]{31:0}
= shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{63:32} = shift_right_unsigned(zero_ext(GR[r
1
GR[r
]{31:0}
= shift_right_signed(sign_ext(GR[r
1
GR[r
]{63:32} = shift_right_signed(sign_ext(GR[r
1
].nat || tmp_nat;
3
] : count
);
2
5
].nat : 0);
2
// two_byte_form
// unsigned shift
shift_count);
shift_count);
shift_count);
shift_count);
// signed shift
shift_count);
shift_count);
shift_count);
shift_count);
// four_byte_form
// unsigned shift
shift_count);
shift_count);
// signed shift
shift_count);
shift_count);
pshr
]{15:0},
16),
3
]{31:16}, 16),
3
]{47:32}, 16),
3
]{63:48}, 16),
3
]{15:0},
16),
3
]{31:16}, 16),
3
]{47:32}, 16),
3
]{63:48}, 16),
3
]{31:0},
32),
3
]{63:32}, 32),
3
]{31:0},
32),
3
]{63:32}, 32),
3
3:225
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