Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1160

tbit — Test Bit
( ) tbit.
Format: qp trel
The bit specified by the
Description:
single bit result either complemented or not depending on the trel completer. This result
is written to the two predicate register destinations
written to the destinations is determined by the compare type specified by ctype. See
the Compare instruction and
The trel completer values .nz and .z indicate non-zero and zero sense of the test. For
normal and unc types, only the .z value is directly implemented in hardware; the .nz
value is actually a pseudo-op. For it, the assembler simply switches the predicate target
specifiers and uses the implemented relation. For the parallel types, both relations are
implemented in hardware.
Table 2-53.
trel
nz
z
Table 2-54.
trel
nz
z
If the two predicate register destinations are the same (
predicate register), the instruction will take an Illegal Operation fault, if the qualifying
predicate is set, or if the compare type is unc.
Volume 3: Instruction Reference
. , = ,
ctype p p r pos
1 2 3 6
immediate is selected from GR r
pos
6
Table 2-15 on page
Test Bit Relations for Normal and unc tbits
Test Relation
selected bit == 1
selected bit == 0
Test Bit Relations for Parallel tbits
Test Relation
selected bit == 1
selected bit == 0
. The selected bit forms a
3
and . The way the result is
p p
1 2
3:39.
Pseudo-op of
z p
and specify the same
p p
1 2
tbit
I16
 p
1 2
3:261