Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1512

IN—Input from Port
Opcode
E4 ib
E5 ib
E5 ib
EC
ED
ED
Description
Copies the value from the I/O port specified with the second operand (source operand)
to the destination operand (first operand). The source operand can be a
byte-immediate or the DX register; the destination operand can be register AL, AX, or
EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively).
Using the DX register as a source operand allows I/O port addresses from 0 to 65,535
to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be
accessed.
When accessing an 8-bit I/O port, the opcode determines the port size; when accessing
a 16- and 32-bit I/O port, the operand-size attribute determines the port size.
At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports.
Here, the upper eight bits of the port address will be 0.
This instruction is only useful for accessing I/O ports located in the processor's I/O
address space.
I/O transactions are performed after all prior data memory operations. No
subsequent data memory operations can pass an I/O transaction.
In the Itanium System Environment, I/O port references are mapped into the
64-bit virtual address pointed to by the IOBase register, with four ports per
4K-byte virtual page. Operating systems can utilize the TLB in the Itanium
architecture to grant or deny permission to any four I/O ports. The I/O port
space can be mapped into any arbitrary 64-bit physical memory location by
operating system code. If CFLG.io is 1 and CPL>IOPL, the TSS is consulted for
I/O permission. If CFLG.io is 0 or CPL<=IOPL, permission is granted
regardless of the state of the TSS I/O permission bitmap (the bitmap is not
referenced).
If the referenced I/O port is mapped to an unimplemented virtual address (via
the I/O Base register) or if data translations are disabled (PSR.dt is 0) a
GPFault is generated on the referencing IN instruction.
Operation
IF ((PE = 1) AND ((VM = 1) OR (CPL > IOPL)))
THEN (* Protected mode or virtual-8086 mode with CPL > IOPL *)
IF (CFLG.io AND Any I/O Permission Bit for I/O port being accessed = 1)
FI;
4:210
Instruction
IN AL, imm8
IN AX, imm8
IN EAX, imm8
IN AL,DX
IN AX,DX
IN EAX,DX
THEN #GP(0);
Description
Input byte from imm8 I/O port address into AL
Input byte from imm8 I/O port address into AX
Input byte from imm8 I/O port address into EAX
Input byte from I/O port in DX into AL
Input word from I/O port in DX into AX
Input doubleword from I/O port in DX into EAX
Volume 4: Base IA-32 Instruction Reference