Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 1214

4.3.1.9 Bit Strings
40
I9
Instruction
popcnt
clz
4.3.2 Integer Shifts
The integer shift, test bit, and test NaT instructions are encoded within major opcode 5
using a 2-bit opcode extension field in bits 35:34 (x
field in bit 33 (x). The extract and test bit instructions also have a 1-bit opcode
extension field in bit 13 (y).
assignments.
Table 4-21.
Opcode
Bits 40:37
5
Most deposit instructions also have a 1-bit opcode extension field in bit 26 (y).
Table 4-22
Table 4-22.
Opcode
Bits 40:37
5
4.3.2.1 Shift Right Pair
40
I10
Instruction
shrp
Volume 3: Instruction Formats
37 36 35 34 33 32 31 30 29 28 27 26
7 z x z v x x
a 2a b e 2c 2b
4 1 2 1 1 2 2
Operands Opcode
r = r
1 3
Table 4-21
Integer Shift/Test Bit/Test NaT 2-bit Opcode Extensions
x x
2
Bits 35:34 Bit 33
0
1
0
2
3
shows these assignments.
Deposit Opcode Extensions
x x
2
Bits 35:34 Bit 33
0
1
1
2
3
37 36 35 34 33 32 27 26
5 x x count
2 6d
4 1 2 1 6
Operands
r = r , r , count
1 2 3
20 19
r 0
3
1 7 7
z z
a b
7 0 1
) and a 1-bit opcode extension
2
shows the test bit, extract, and shift right pair
0
Test Bit (Table 4-23)
extr.u I11
0
Test Bit/Test NaT/Test Feature
dep.z I12
dep – imm
20 19
r r
3 2
7 7
Opcode
5
6
13 12 6 5
r
1
7
Extension
v x x x
e 2a 2b
0 1 1
y
Bit 13
1
Test NaT/Test Feature
extr I11
shrp I10
y
Bit 26
1
(Table 4-23)
dep.z – imm
8
I14
1
13 12 6 5
r
1
7
Extension
x x
2
3 0
0
qp
6
2c
2
3
(Table 4-23)
I13
0
qp
6
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