Intel ITANIUM ARCHITECTURE 2.3 Manuals

Manuals and User Guides for Intel ITANIUM ARCHITECTURE 2.3. We have 1 Intel ITANIUM ARCHITECTURE 2.3 manual available for free PDF download: Manual

INTEL ITANIUM ARCHITECTURE 2.3 Manual

INTEL ITANIUM ARCHITECTURE 2.3 Manual (1898 pages)

Brand: INTEL | Category: Software | Size: 11 MB

Table of Contents

Table of Contents
4
1 About this Manual

14
2 Introduction to the Intel Itanium Architecture

24
- Introduction to the Intel ® Itanium ® Architecture
  24
- Operating Environments
  24
- Instruction Set Transition Model
  25
- System Environment
  25
  - Major Operating Environments
    25
  - Instruction Set Features
    26
- Instruction Level Parallelism
  26
- Compiler to Processor Communication
  27
- Control Speculation
  27
- Speculation
  27
  - Data Speculation
    28
  - Predication
    28
- Register Stack
  29
- Branching
  30
- Floating-Point Architecture
  30
- Register Rotation
  30
- Multimedia Support
  31
- Terminology
  32
- Application Register State
  34
3 Execution Environment

34
- Reserved and Ignored Registers and Fields
  34
6 IA-32 Application Execution Model in an Intel Itanium

120
- IA-32 Execution Layer
  120
- Hardware-Based IA-32 Application Execution
  120
- Instruction Set Modes
  121
- Instruction Set Transition Model
  121
- Instruction Set Mode Transitions
  124
- Application Registers
  124
- IA-32 Application Register Model
  125
- IA-32 Application Register Mapping
  126
- IA-32 General Registers (GR8 to GR15)
  128
- IA-32 Segment Register Selector Format
  129
- IA-32 Code/Data Segment Register Descriptor Format
  129
- IA-32 Segment Register Fields
  129
- IA-32 Environment Initial Register State
  131
- IA-32 Environment Runtime Integrity Checks
  133
- EFLAG Register (AR24)
  134
- IA-32 EFLAGS Register Fields
  135
- IA-32 Floating-Point Register Mappings
  136
- IA-32 Floating-Point Control Register (FCR)
  138
- Floating-Point Data Register (FDR)
  140
- Floating-Point Instruction Register (FIR)
  140
- SSE Registers (XMM0-XMM7)
  141
- Memory Addressing Model
  142
- Part II: Optimization Guide for the Intel
  146
  - Overview of the Optimization Guide
    148
  - Introduction to Programming for the Intel ® Itanium ® Architecture
    150
- Overview
  150
- Registers
  150
- Using Intel ® Itanium ® Instructions
  151
- Format
  151
- Expressing Parallelism
  151
- Bundles and Templates
  152
- Memory Access and Speculation
  153
- Functionality
  153
- Control Speculation
  153
- Predication
  154
- Data Speculation
  154
- Architectural Support for Procedure Calls
  155
- Stacked Registers
  155
- Register Stack Engine
  155
- Branches and Hints
  155
- Branch Instructions
  156
- Loops and Software Pipelining
  156
- Rotating Registers
  156
- Summary
  157
3 Memory Reference

158
2 Introduction to Programming for the Intel Itanium

158
- Overview
  158
- Non-Speculative Memory References
  158
- Stores to Memory
  158
- Loads from Memory
  158
- Data Prefetch Hint
  159
- Instruction Dependencies
  159
- Control Dependencies
  159
- Data Dependencies
  160
- Control Dependency Preventing Code Motion
  160
- Itanium ® Architecture
  161
- Using Data Speculation in the Intel Architecture
  163
- Combining Data and Control Speculation
  167
- Minimizing Code Size During Speculation
  170
- Using a Single Check for Three Advanced Loads
  172
- Flow Graph Illustrating Opportunities for Off-Path Predication
  178
- Software Pipelining and Loop Support
  192
- Ctop and Cexit Execution Flow
  198
- Ctop Loop Trace
  199
- Wtop and Wexit Execution Flow
  200
- Wtop Loop Trace
  202
- Floating-Point Applications
  216
- Software Divide/Square Root Sequence
  222
- Computational Models
  223
- Multiple Status Fields
  224
- Other Features
  225
- Memory Access Control
  227
- Summary
  228
- Itanium Architecture
  231
- Part I: Application Architecture Guide
  233
- Part 2: Optimization Guide for the Intel® Itanium® Architecture
  233
- Index
  239
- System Environment
  261
- Relationship between Instruction Type and Execution Unit Type
  897
- Template Field Encoding and Instruction Slot Mapping
  897
- Intel ® Itanium ® Architecture Software Developer's Manual Rev
  1191

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